Assembly and Reliability Assessment of Lithography-Based Wafer-Level Compliant Chip-to-Substrate Interconnects
Submitted by Caspar_admin on Fri, 01/03/2014 - 21:29Citation:
Kacker, K., Lo, G., and Sitaraman, S. K., "Assembly and Reliability Assessment of Lithography-Based Wafer-Level Compliant Chip-to-Substrate Interconnects," 55th Electronic Components and Technology Conference, IEEE-CPMT and EIA, Orlando, FL, May 2005, pp. 545-550.