Chip Scale Polymer Stud Grid Array Packaging and Reliability Based on Low Cost Flip-Chip Processing
Submitted by Caspar_admin on Fri, 01/03/2014 - 21:55Citation:
Paydenkar, C. S., Baldwin, D. F., Sitaraman, S., Wong, C. P., and Lewis, B. J., “Chip Scale Polymer Stud Grid Array Packaging and Reliability Based on Low Cost Flip-Chip Processing,” 50th Electronic Components and Technology Conference, IEEE-CPMT and EIA, Las Vegas, NV, May 2000, pp. 1449-1459.